High speed microprocessors may require clock signals in which duty cycle is tightly controlled. Duty cycle refers to the percentage of time a clock signal is "high" versus "low". In microprocessor applications, it might be desired for the clock signal to have a 50% duty cycle as illustrated in FIG. 1. In practical implementation, a clock signal with a 45%-55% duty cycle may be acceptable. Clock signals with imbalanced duty cycles beyond that range may introduce timing errors in a microprocessor system.
FIG. 2 illustrates a portion of a prior art PLL clock generator design using a typical technique for generating a clock with a substantially balanced duty cycle. In PLL 100 of FIG. 1, a current controlled oscillator 110 may be used to generate a clock at twice (2x) frequency of the processor, where x is the processor clock frequency. The 2x clock may then be divided by two in divider 120, producing a clock signal with a balanced duty cycle of approximately 50%.
A portion of the output of divider 120 may be fed back to phase frequency detector/charge pump 140 which in turn may compare this clock to a reference signal 190 and charge or discharge filter 150 in such a way as to equalize the phase and frequency of the reference and fed back clocks. Control voltage VCTRL is equal to supply voltage Vdd minus voltage VCAP across filter 150. Control voltage VCTRL may in turn be fed to voltage to current converter 130 to produce control current I. Note that other arrangements for filter 150 are also possible. For example, filter 150 may be referenced to ground instead of Vdd or a different type or order of filter may be used. As illustrated in FIG. 2, filter 150 may include a capacitance and a resistance.
Control current I may in turn control the frequency output of current controlled oscillator (CCO) 110. The use of divider 120 insures that the resultant clock signal will have a substantially balanced duty cycle.
However, the apparatus of FIG. 2 requires that a clock signal be generated at a frequency twice the design frequency of the system. At such high frequencies, phase jitter may become a problem due to worsened power supply rejection of the CCO. FIG. 3 is a graph illustrating power supply sensitivity of an oscillator.
On the X-axis of FIG. 3, control voltage VCAP is illustrated. On the Y-axis, corresponding clock frequency is illustrated. The upper, solid line curve illustrates the relationship between frequency and control voltage at a first power supply voltage Vdd=2.0 Volts. The lower, dotted line curve illustrates the relationship between frequency and control voltage at a second power supply voltage Vdd=1.6 Volts. The supply voltages Vdd in FIG. 3 are by way of example only and should not be construed as limiting the scope of the present invention in any way.
As illustrated in FIG. 3, frequency output from an oscillator may vary with changes in supply voltage. When designing a clock generator for a computer system, a designer must take into consideration potential changes in supply voltage due to temperature, load, ripple voltage, and the like. If supply voltage Vdd changes from 2.0 to 1.6 volts, oscillator frequency output may change accordingly, particularly at higher frequencies. Such changes in oscillator frequency may be cause frequency jitter and create timing problems within a processor.
As illustrated in FIG. 3, for a given oscillator design, power supply sensitivity may not be a problem below a particular threshold, for example 500 MHz. Thus, an oscillator operating below such frequencies may be relatively insensitive to changes in power supply voltage. However, if a processor is to operate at, for example, 400 MHz, a 2x oscillator frequency of 800 MHz may be required. At such frequencies, power supply sensitivity may become a problem.
Thus it would be desirable to have a PLL clock generator design in which the oscillator (VCO or CCO) operates at the frequency of the processor and not twice (2x) the frequency.